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Design for Environment
Design for Environment
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Design
Advanced Design System
Urban design
Sustainable design
Design engineer
Electronic design automation software
Circuit simulation
Mentor Graphics
Advanced Design System
Hardware description languages
(38)
Systemverilog
Verilog
Vhdl
A Block diagram Language
Altera Hardware Description Language
Altera Hardware Description Language
Averest
Delta delay
ELLA (programming language)
Esterel Studio
Handel-C
Hardware description language
Hardware verification languages
IEEE 1076
IEEE 1164
Icarus Verilog
Interoperable PDK Libraries
JHDL
List of Verilog simulators
Lola (hardware description language)
Lustre (programming language)
MyHDL
Numeric std
Open Verification Library
PALASM
Property Specification Language
Register transfer notation
Ruby (hardware description language)
SpecC
SyncCharts
System description languages
SystemTCL
Systemc
Systemverilog DPI
Tensilica Instruction Extension
Transaction-level modeling
VHDL-AMS
Verilog-A
Verilog-AMS
more...
Environmental design
Sustainable design
See also
(20)
Integrated Design Environment
Built environment
Biodiversity
Conservation movement
Design Impact Measures
Design Impact Measures
Environmental movement
Industrial ecology
Leadership in Energy and Environmental Design
Natural environment
Nature
Sustainability
Sustainable Building Alliance
Run time (computing)
Systemc
The Design
Oracle Database
Virtual environment
Fpga
Building design
Estimation of distribution algorithm
more...
